Resistive memory materials can be used to construct memory cells in which one bit of information, i.e., a logic “1” or “0”, is in each case represented by different electrical resistance values.
In recent years, phase change materials have been investigated, in particular, which can be brought to crystalline or amorphous phase states having different electrical resistances by heating. Typical phase change materials, such as those used in CDs and DVDs, are made of chalcogenides. Chalcogenides are distinguished in particular by the fact that their electrical resistance changes by several orders of magnitude if a change in the phase state between the amorphous phase and the crystalline phase is induced. A change in the phase state can be brought about via Joule heat, for example, by application of electric currents. By contrast, in polymer memory cells, the excitability of specific proteins, such as bacteriorhodopsin, embedded in a polymer layer is utilized for storing items of information, each alteration of the state of the proteins being accompanied by a different electrical resistance of the layer.
The current-voltage characteristic of such a polymer memory cell is shown, for example, in FIG. 1. In this case, the logic values “0” and “1” are represented by different electrical resistance values RC0 and RC1, respectively, of the memory cell. The two resistance values correspond to the high-resistance and the low-resistance straight line, respectively, in the current-voltage characteristic.
In the example of FIG. 1, a logic “0” is written by application of a voltage of +1V, wherein a logic “1” is written by application of a voltage of −1V. Writing to a resistive memory cell is also referred to as “programming” of the memory cell. If the state of the memory cell is intended to be read, a read voltage is applied whose value lies below the voltages for writing to the memory cell, in order to avoid an inadvertent reprogramming of the memory cell. In the present example, a read voltage of 0.5 V is applied and, in accordance with the different resistance values RC0 and RC1, a high and low current are respectively measured in order to detect the logic values “0” and “1”.
A typical NOR architecture of a memory arrangement comprising a plurality of resistive memory cells is shown in FIGS. 2A, 2B and 2C. In this case, each resistive memory cell 1 is connected, on the one hand, via the source-drain path of a MOS memory cell selection transistor 2 to a bit line (BL). On the other hand, each resistive memory cell 1 is connected to a so-called cell plate or cell plate line 3 for applying a reference potential. The reference potential is applied as a reference point with respect to the potential of the bit line. Furthermore, each MOS memory cell selection transistor is connected via its gate terminal to a word line (WL) for the control thereof.
FIGS. 2A to 2C illustrate examples of writing and reading operation of a resistive memory cell in the NOR architecture. FIG. 2A schematically illustrates a first writing method. Accordingly, a fixed voltage of 1 V, for example, is present at the cell plate line 3, and different operating voltages of 0 V and 2 V, for example, are applied to the bit line for the purpose of switching the resistive memory cell 1 into the different states. In a second writing method, which is illustrated schematically in FIG. 2B, voltage is applied to the cell plate line 3 in a complementary manner with respect to the bit line, where in a case in which, for example, 0 V is applied to the bit line and, for example, 1 V is applied to the cell plate. Meanwhile, in a case wherein, for example, 1 V is applied to the bit line, for example, 0 V is applied to the cell plate. FIG. 2C illustrates the reading operation. Accordingly, the programmed state of a resistive memory cell 1 can be read via a reference voltage of 0 V, for example, being applied to the cell plate line 3, while a read voltage of 0.5 V, for example, is applied to the bit line.
In order to select the resistive memory cell 1 for writing or reading, the word line connected to the MOS memory cell selection transistor 2 of the selected memory cell 1 is put at 3 V, for example, during the reading or writing operation in order to put the associated MOS memory cell selection transistor 2 into its ON state, while the rest of the word lines are put at 0 V, for example, with the result that the associated MOS memory cell selection transistors 2 are in their OFF state.
FIGS. 3A and 3B schematically show a sectional illustration and plan view, respectively, associated with this typical NOR architecture of memory elements. Accordingly, for example, n+-doped source regions 4 and likewise n+-doped drain regions 5 are provided in the surface of a p-conducting semiconductor body. The drain regions 5 are in each case connected to the bottom electrodes 7 of resistive memory cells 1 via contact plugs 6 composed of polycrystalline silicon, for example. Consequently, a resistive memory material 9 is on the one hand connected to a drain region 5, while on the other hand it is connected to a cell plate line 3, which simultaneously acts as top electrode of the resistive memory cell 1. Respective word lines WL are arranged in a position disposed opposite channel zones (not specifically shown here) that are arranged between the source and drain regions and serve for controlling the MOS memory cell selection transistors. Furthermore, each source region 4 is connected to a bit line BL via contact plugs 8. As can be gathered from FIG. 3A, in particular, a source region 4 is in each case associated with a pair of drain regions 5, two adjacent pairs of drain regions 5 being insulated from one another by STI (Shallow Trench Isolation) trenches 10. Furthermore, the structures above the semiconductor plate are embedded in a dielectric material (not specifically illustrated) composed of SiO2, for example. Only the bit line BL is illustrated in FIG. 3B, while the plate line (not illustrated) is to be imagined as running above the bit line. In FIG. 3B, the insulation clearance between contact plug and bit line is indicated by a dashed square around the contact plugs 6 connecting the MOS memory cell selection transistors to the memory cells.
In the conventional NOR architecture, the resistive memory cell 1 and the cell plate line 3 are arranged the furthest away from the surface of the semiconductor body having the source and drain regions. It is conventional or standard that the word and bit lines are led perpendicular to one another, which has the consequence of the bit lines having to be led parallel to the cell plate lines. However, a minimum circuit layout is not possible in this arrangement. Rather, the minimum area per memory cell (memory cell area) that can be achieved in the conventional NOR architecture is at best approximately 9 F2, where F denotes the minimum feature size of the technology used for producing the circuit structures.
A further reduction of the minimum memory cell area that can be achieved is extremely desirable, primarily with regard to advancing miniaturization and an increase in performance of memory components.